The present invention relates to a gap coupling type bus system for carrying out fast data transfer between functional components in an information processing unit.
As the conventional gap coupling (directional coupling) type bus system, there is such a bus system shown as non-contact type bus wiring described in Japanese Unexamined Patent Laid-Open No. 7-141079.
In this non-contact type bus wiring described in 7-141079, the bus system includes one and only bus master and many bus slaves. Each transmission line of the bus system shown in this literature is not connected directly with another line. Signal that passes one transmission line induces another transmission line to generate signal in that transmission line through so-called xe2x80x9ccross talk noisexe2x80x9d generation mechanism via inductive and capacitive couplings with predefined gaps. The latter signal, which is essentially cross talk noise, is demodulated to complete data transfer. To this end, the wiring is so constructed that the transmission line extended from the single bus master is terminated by a terminating resistor at its far end, and transmission lines connected to the plurality of bus slaves run.a certain length in parallel with the former transmission line.
Signal outputted from the bus master induces signal in every transmission line connected to respective bus slave, owing to the so-called xe2x80x9ccross talk noisexe2x80x9d generation mechanism, thus providing the same data to each bus slave.
On the other hand, signal outputted from a bus slave onto the transmission line connected thereto, induces signal in the transmission line connected to the bus master, owing to the cross talk noise generation mechanism. The bus master demodulates this signal to complete data transfer.
As described above, the non-contact type bus wiring described in 7-141079 can transfer data between a bus master and a plurality of bus slaves.
Now, data transfer among all the modules on a bus has become an ordinary matter, and, in terms of the non-contact bus wiring described in the above-mentioned 7-141079, data transfer from one bus slave to another bus slave is a prerequisite for employing the bus system in an information processing unit.
However, direct data transfer among the bus slaves has been difficult, since the transmission lines of the bus slaves are arranged to be connected indirectly with one another via the transmission line of the bus master. Namely, signal, i.e. so-called xe2x80x9ccross talk noisexe2x80x9d, induced on the transmission line connected to the bus master is small in its amplitude, and even when this signal generates another signal on a transmission line connected to another bus slave, through cross talk noise generation mechanism, the resultant signal amplitude is minimum. To demodulate this signal, it is too small in its amplitude relatively to swing of power supply potential or with unnecessary radiant noise. Further, it is difficult for a demodulator circuit mounted on a bus slave or the bus master to attain required sensitivity. Thus, the prior art system is not suitable for data transfer between bus slaves, or, in other words, modern data transfer between all modules connected to a bus system.
Further, clock distribution in the conventional bus topology using, for example, TTL has its limit at some dozen MHz.
Accordingly, an object of the present invention is to provide a gap coupling type bus system that permits the mutual data transfer among all modules connected to a bus.
Another object of the present invention is to provide a gap coupling type bus system that can speed up clock distribution in bus topology.
A gap coupling type bus system according to the present invention is characterized in that it comprises, for at least three modules, each module being provided with at least one sending/receiving circuit for sending and receiving a signal: at least three signal lines respectively connected to the at least three modules, and terminating resistors connected to respective signal lines at the other ends of the signal lines, each terminating resistor having generally same value as characteristic impedance of the signal line, wherein the at least three signal lines have portions laid in parallel with one another with a predetermined gap, correspondingly to every combination of different two modules out of the at least three modules.
According to this construction, since, for each combination of different two modules out of at least three modules, there is a coupled portion via a gap, mutual data transfer is permitted between any modules, without having one as a master.
In this construction, the at least three signal lines are laid in a generally netlike pattern, by, for example, crossing one another in grade separation. In that case, it is preferable that said signal lines are laid in parallel at portions of crossing in grade separation. This realizes good gap couplings at those portions.
For example, the at least three modules are arranged in a line; the terminating resistors corresponding to these modules are arranged in parallel with the line of the modules at a distance from the modules; and each signal line is laid in a meander shape between each module and a corresponding one of the terminating resistor.
By such construction, each module can identify a module that outputted data, depending on difference in data arrival times.
In one embodiment, all the bus modules are arranged in a line (assumed to be a longitudinal direction), and signal lines connected to respective modules are drawn out laterally. When there are four bus modules for example, 1st and 2nd signal lines of those drawn-out signal lines are coupled via a gap, and 3rd and 4th are coupled via a gap, just after the drawing out. Next, before further drawing out the lines laterally, their order is changed to 2nd, 1st, 4th, and 3rd in the longitudinal direction, and after the drawing out, 1st and 4th are coupled via a gap. Before continuing to draw out laterally, their order is changed to 4th, 2nd, 3rd, and 1st, and after the drawing out, 2nd and 3rd are coupled via a gap. After the above couplings via a gap, the signal lines are connected to respective terminating resistors, to form a netlike pattern.
By thus forming the signal lines in a netlike pattern, every signal line can be coupled with all the other signal lines via gap, and data transfer between any bus modules can be realized.
As described above, the signal lines are laid in parallel with each other at a portion of grade separation. However, the signal lines may be laid such that, at some portions of the grade separation, the signal lines cross each other at a right angle. By this, wiring length contributing to that gap coupling between the signal lines becomes the minimum, and signal induced by the cross talk generating mechanism is very small. Thus, it is possible to use grade separation without accompanying the gap coupling, and wiring flexibility is enhanced.
Other gap coupling type bus system of the present invention is characterized in that each module and each terminating resistor corresponding to that module positioned at both ends of each signal line are arranged adjacently, and each of the at least three signal lines is laid in a loop or fold structure from the relevant module to the terminating resistor corresponding to that module.
For example, the at least three modules are arranged generally in a line, and the signal line of each module has portions laid in parallel with and adjacently to other signal lines successively in mid course of the wiring in the loop or fold structure from its own sending/receiving circuit to the corresponding terminating resistor.
In such construction, total length of each signal line in the loop or fold structure is generally same for any of the modules, and total length from a sending/receiving circuit of one module through the portions laid in parallel and adjacently, to a sending/receiving circuit of other module is generally same for every case.
By this, data outputted from whichever module arrives at target modules at the same time (simultaneous arrival). By this, data transfer cycle can be determined by delay time from start time of outputting signal to arrival and the number of repeated cycles for data. Thus, it is possible to easily realize a simple bus protocol, similarly to the conventional bus.
Still other gap coupling type bus system of the present invention is characterized in that, it comprises, for at least three modules, each module being provided with at least one sending/receiving circuit for sending and receiving a signal: at least three signal lines respectively connected to the at least three modules; and terminating resistors connected to respective signal lines at other ends of the signal lines, each terminating resistor having generally same value as characteristic impedance of the signal line; wherein, one of the at least three signal lines is a basic signal line, and signal lines of the modules other than the basic signal line are successively laid in parallel with the basic signal line with a predetermined gap to form stubs, and total length from a module having the basic signal line through the portion laid in parallel, and through other signal line forming the stub, to the other module is generally same, for any ones of the other modules.
By this construction of the present invention, it is possible to attain wiring of true bus topology having high speed property and constant propagation delay time for signals. In particular, it is possible to speed up clock distribution in the bus topology.
Other gap coupling type bus system according to the present invention is characterized in that, in the above-described bus system, the signal line connected with the sending/receiving circuit has two distribution conductors, a sending circuit of said sending/receiving circuit outputs an equivalent onto one of said two distribution conductors, and an inverted value onto the other of the two distribution conductors, depending on a logical value of an input of the sending/receiving circuit, and a receiving circuit of the sending/receiving circuit takes a form of a differential circuit that receives, as inputs, the equivalent of one of the two distribution conductors and the inverted value of the other, and outputs the logical value after demodulation.
Thus, by using two distribution conductors in a pair, as a signal line, and forming differential circuit, with one polarity being inverted, input amplitude of the differential circuit of the receiving side module is expanded to twice as large as the original amplitude, and designed sensitivity of the differential circuit can be relaxed. Further, even when the center of amplitude, i.e. ground potential swings due to some factor, the differential circuit can demodulate the signals without depending on the ground potential, and thus has an excellent noise insulating characteristic.